Descripción
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Dynamic thermal management techniques require a collection of on-chip thermal sensors that imply a significant area and power overhead. Finding the optimum number of temperature monitors and their location on the chip surface to optimize accuracy is an NP-hard problem. In this work we improve the modeling of the problem by including area, power and networking constraints along with the consideration of three inaccuracy terms: spatial errors, sampling rate errors and monitor-inherent errors. The problem is solved by the simulated annealing algorithm. We apply the algorithm to a test case employing three different types of monitors to highlight the importance of the different metrics. Finally we present a case study of the Alpha 21364 processor under two different constraint scenarios. | |
Internacional
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Si |
Nombre congreso
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Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on |
Tipo de participación
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960 |
Lugar del congreso
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Sevilla |
Revisores
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Si |
ISBN o ISSN
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978-1-4673-0685-0 |
DOI
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10.1109/SMACD.2012.6339419 |
Fecha inicio congreso
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19/09/2012 |
Fecha fin congreso
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21/09/2012 |
Desde la página
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69 |
Hasta la página
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72 |
Título de las actas
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Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on |