Observatorio de I+D+i UPM

Descripción
One of the main challenges in PowerSoC converters is the integration of the output capacitor. In some applications, the minimum value of the capacitance is constrained not by the maximum allowed voltage ripple but by dynamic requirements. This paper investigates for a 10 MHz Buck converter if the design of very fast controls can reduce the required output capacitor and which controls are more suitable. It is also analyzed the effect that the moment in which the load transient can occur has on the reduction of the size of the output capacitor.
Internacional	Si
Nombre congreso	Integrated Power Systems (CIPS), 2014 8th International Conference on
Tipo de participación	960
Lugar del congreso
Revisores	Si
ISBN o ISSN	978-3-8007-3578-5
DOI
Fecha inicio congreso	25/02/2014
Fecha fin congreso	27/02/2014
Desde la página	1
Hasta la página	6
Título de las actas	Impact of the control on the size of the output capacitor in the integration of Buck converters

Esta actividad pertenece a memorias de investigación

• Autor: Jorge Cortés González (UPM)
• Autor: Vladimir Svikovic . (UPM)
• Autor: Pedro Alou Cervera (UPM)
• Autor: Jesus Angel Oliver Ramirez (UPM)
• Autor: Jose Antonio Cobos Marquez (UPM)

• Creador: Grupo de Investigación: Electrónica Industrial
• Centro o Instituto I+D+i: Centro de Electrónica Industrial. CEI