Observatorio de I+D+i UPM

Descripción
In this work we propose a Ring Oscillator PUF focused on the variability of the duty cycle instead of measuring the output frequency deviations. To achieve this goal, we replace the common ring oscillators, whose outputs are clock signals of 50% duty cycle, for ring oscillators with an asymmetric structure. The asymmetry confers the ability to configure the duty cycle of each individual node. Through the measurement of a relative value, such as the duty cycle, the robustness of the PUF is improved. For example, the output shift due to the temperature variation is decreased from 3% to less than 0,5%. Moreover, the potential input challenges are multiplied by the number of stages of each ring oscillator. Hence, with our design, the number of ring oscillators needed to build a robust PUF is decreased thanks to the addition of multiple and uncorrelated variables but with negligible area overhead.
Internacional	Si
Nombre congreso	IEEE International Symposium on Circuits and Systems (ISCAS), 2016
Tipo de participación	970
Lugar del congreso	Montreal, Canadá
Revisores	Si
ISBN o ISSN	2379-447X
DOI	10.1109/ISCAS.2016.7539093
Fecha inicio congreso	22/05/2016
Fecha fin congreso	25/05/2016
Desde la página	2471
Hasta la página	2474
Título de las actas	Circuits and Systems (ISCAS), 2016 IEEE International Symposium on

Esta actividad pertenece a memorias de investigación

• Autor: M. Luisa Lopez Vallejo (UPM)
• Autor: Javier Agustin Saenz (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Centro o Instituto I+D+i: Centro de I+d+i en Procesado de la Información y Telecomunicaciones
• Departamento: Ingeniería Electrónica