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Descripción
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| Traditional FPGA design workflow requires the complete system in order to perform timing characterization. However, high-performance digital systems implementing scientific applications frequently occupy a large area and are suitably developed following a latency insensitive design approach to achieve multi-level parallelism. The produced circuits are composed of several deeply pipelined specialized computational macroblocks and try to maximize both the operating frequency and the usage of FPGA device resources to full capacity. These goals are most appropriately attainable through a decentralized control strategy and the optimization of performance for individual blocks independently from each other. This work proposes a synthesizable virtual wrapper architecture which does not add any functionality but simulates complete system conditions for the timing characterization of individual blocks using standard low-level synthesis tools. It further presents a high-level tool to generate both the computational blocks and the wrapper from a functional specification in C language, and shows that large blocks with inputs and outputs exceeding the available number of FPGA pins can be automatically generated and characterized. In particular, results for the blocks generated for a real computational fluid dynamics application are provided. | |
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Internacional
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Si |
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Nombre congreso
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28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS'18 |
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Tipo de participación
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960 |
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Lugar del congreso
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Platja D'Aro, Girona (España) |
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Revisores
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Si |
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ISBN o ISSN
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978-1-5386-6365-3 |
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DOI
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Fecha inicio congreso
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02/07/2018 |
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Fecha fin congreso
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04/07/2018 |
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Desde la página
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7 |
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Hasta la página
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12 |
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Título de las actas
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Proceedings of the 28th International Symposium on Power and Timing Modeling, Optimization and Simulation |