Memorias de investigación
Artículos en revistas:
DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping
Año:2019

Áreas de investigación
  • Ingenierías,
  • Tecnología electrónica y de las comunicaciones,
  • Ciencias de la computación y tecnología informática

Datos
Descripción
Heterogeneous Multiprocessor Systems-on-a-Chip (MPSoCs) with programmable hardware acceleration are currently gaining market share in the embedded device domain. Largest MPSoCs combine several software processing cores with programmable logic. In these systems, reaching the optimal implementation performance is difficult because many manual and time-consuming steps are required to build, from the application specification, a prototype with measurable performances. In this paper, a method is developed that, based on state-of-the-art tools and High-Level Synthesis, deploys within less than an hour a whole hardware-software rapid prototype from a unique dataflow-based application representation: DAMHSE (DAtaflow Method for Hardware/Software Exploration). A human-driven Design Space Exploration (DSE) is conducted in order to find the most performing architectural solution, and compilable/synthesizable code is generated. The method has been tested on an image processing system with software and hardware parallelism. Results show that the obtained absolute performance (pixel/cycles) reaches state-of-the-art, and that DAMHSE leads to a heterogeneous system where performance increases significantly when the application is granted with more hardware resources. One of the greatest challenges in creating such a design automation method resides in the application behavior that may change over time and affect application concurrency and system performance. In order to overcome this problem, the design-time DAtaflow Method for Hardware/Software Exploration (DAMHSE) method is complemented with a runtime application management system that dynamically dispatches jobs (tasks) among the available processing elements (CPUs and/or hardware accelerators). Experimental results show that the performance penalty due to runtime application mapping and scheduling is limited and that the computational performance of the adaptive system remains high. Apart from the vendor-specific HLS, the tools and the frameworks used by the proposed method are open source and tutorials are available to reproduce the results.
Internacional
Si
JCR del ISI
Si
Título de la revista
Microprocessors And Microsystems
ISSN
0141-9331
Factor de impacto JCR
1,161
Información de impacto
Volumen
71
DOI
10.1016/j.micpro.2019.102882
Número de revista
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0
Hasta la página
13
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Participantes
  • Autor: Leonardo Suriano . UPM
  • Autor: Florian Arrestier Univ Rennes, INSA Rennes, IETR UMR CNRS 6164, France
  • Autor: Alfonso Rodriguez Medina UPM
  • Autor: Julien Heulor Univ Rennes, INSA Rennes, IETR UMR CNRS 6164, France
  • Autor: Karol Desnos Univ Rennes, INSA Rennes, IETR UMR CNRS 6164, France
  • Autor: Maxime Pelcat Institut Pascal, UMR CNRS 6602, France
  • Autor: Eduardo de la Torre Arnanz UPM

Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Centro o Instituto I+D+i: Centro de Electrónica Industrial. CEI
  • Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial