Memorias de investigación
Research Publications in journals:
Implementing FFT-Based Digital Channelized Receivers on FPGA Platforms
Year:2008

Research Areas
  • Processing and signal analysis

Information
Abstract
This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.
International
Si
JCR
Si
Title
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS
ISBN
0018-9251
Impact factor JCR
0,938
Impact info
Volume
44
10.1109/TAES.2008.4667732
Journal number
4
From page
1567
To page
1585
Month
OCTUBRE
Ranking
Participants

Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Microondas y Radar
  • Departamento: Señales, Sistemas y Radiocomunicaciones
  • Departamento: Ingeniería Electrónica
  • Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Grupo de Investigación: Grupo de Dispositivos Semiconductores del ISOM