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Descripción
This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.
Internacional	Si
JCR del ISI	Si
Título de la revista	IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS
ISSN	0018-9251
Factor de impacto JCR	0,938
Información de impacto
Volumen	44
DOI	10.1109/TAES.2008.4667732
Número de revista	4
Desde la página	1567
Hasta la página	1585
Mes	OCTUBRE
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Esta actividad pertenece a memorias de investigación

• Autor: Miguel Angel Sanchez Garcia (UPM)
• Autor: M. Luisa Lopez Vallejo (UPM)
• Autor: Jesus Grajal De la Fuente (UPM)
• Autor: Mario Garrido Galvez (UPM)

• Creador: Grupo de Investigación: Microondas y Radar
• Departamento: Señales, Sistemas y Radiocomunicaciones
• Departamento: Ingeniería Electrónica
• Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Grupo de Investigación: Grupo de Dispositivos Semiconductores del ISOM