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Abstract
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| In this paper, a portable hardware design implementing a Fast Fourier Transform oriented to its reusability as a core is presented. The module has been developed using radix-2 Decimation-In-Time algorithm. Structural modeling is implemented using VHDL to describe, simulate and perform the design. The module is portable among different EDA tools and technology independent. It has been synthesized with Quartus II from Altera and ISE from Xilinx. The detailed performance results are presented, as well as a comparison between these and the results provided by Altera and Xilinx FFT IP cores. These show that the proposed design produces better results in the use of physical resources but worsens throughput when compared against the commercial ones. Besides, the IP core from Xilinx shows better throughput than Alteras’s but at a higher implementation cost. | |
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International
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Si |
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Book Edition
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0 |
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Book Publishing
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ISBN
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978-0-7695-3474-9 |
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Series
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Book title
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ReConFig’08. 2008 International Conference on Reconfigurable Computing and FPGAs |
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From page
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337 |
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To page
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342 |