Memorias de investigación
Communications at congresses:
An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithm
Year:2008

Research Areas
  • Electronics engineering

Information
Abstract
In this work we present an FPGA implementation of a single-precision °oating-point arith- metic powering unit. Our powering unit is based on an indirect method that transforms xy into a chain of operations involving a logarithm, a multiplication, an exponential function and dedicated logic for the case of a negative base. This approach allows to use the full input range for the base and exponent without limiting the range of the exponent as in direct methods. A tailored hardware implementation is exploited to increase the accuracy of the unit reducing the relative errors of the operations while high performance is obtained taking advantage of the FPGA capabilities for parallel architectures. A careful design of the pipeline stages of the involved operators allows a clock cycle of 201.3 MHz on a Xilinx Virtex-4 FPGA.
International
Si
Congress
8th Conference on Real Numbers and Computers
960
Place
Santiago de Compostela (Spain)
Reviewers
Si
ISBN/ISSN
978-84-691-4381-0
Start Date
07/07/2008
End Date
09/07/2008
From page
68
To page
77
Proceedings 8th Conference on Real Numbers and Computers (RNC8)
Participants

Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica