|
Descripción
|
|
|---|---|
| This work is oriented towards the high-level dynamic power estimation of DSP-oriented designs implemented in a chosen target hardware architecture. According to the different power features of logic and communication design segments, the presented power estimation methodology includes two different models. One is used for power estimation of the global routing employed for interconnections between the components. The other is used for both, local interconnect and logic, power estimation of the components. The complete methodology in this work has been applied to DSP circuits implemented in modern Field Programmable Gate Array devices (FPGAs). | |
|
Internacional
|
Si |
|
ISBN
|
|
|
Tipo de Tesis
|
Doctoral |
|
Calificación
|
Sobresaliente cum laude |
|
Fecha
|
02/10/2009 |