Observatorio de I+D+i UPM

Descripción
Current trend on FPGAs is to increase the number of inputs of the LUT up to six inputs to improve resource utilization. In this work we have analyzed the impact of the inputs expansion in two different architectures, memory-based and multiplexer-based, considering area, performance and power. A new memory-based architecture is presented based on the use of a 7-transistor cell and dedicated reading and writing circuits. The experimental results carried out demonstrate that for a six input LUT, our architecture outperforms the traditional multiplexer-based LUT, which is commonly considered the optimum architecture.
Internacional	Si
Nombre congreso	IEEE International Conference on Electronics, Circuits and Systems, ICECS
Tipo de participación	960
Lugar del congreso	Tunisia
Revisores	Si
ISBN o ISSN	978-1-4244-5091-6
DOI
Fecha inicio congreso	13/12/2009
Fecha fin congreso	16/12/2009
Desde la página	423
Hasta la página	426
Título de las actas	2009 16th IEEE International Conference On Electronics, Circuits and Systems

Esta actividad pertenece a memorias de investigación

• Autor: Pedro Echevarria Aramendi (UPM)
• Autor: M. Luisa Lopez Vallejo (UPM)
• Autor: Carlos Alberto Lopez Barrio (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Departamento: Ingeniería Electrónica