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Descripción
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| Current trend on FPGAs is to increase the number of inputs of the LUT up to six inputs to improve resource utilization. In this work we have analyzed the impact of the inputs expansion in two different architectures, memory-based and multiplexer-based, considering area, performance and power. A new memory-based architecture is presented based on the use of a 7-transistor cell and dedicated reading and writing circuits. The experimental results carried out demonstrate that for a six input LUT, our architecture outperforms the traditional multiplexer-based LUT, which is commonly considered the optimum architecture. | |
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Internacional
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Si |
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Nombre congreso
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IEEE International Conference on Electronics, Circuits and Systems, ICECS |
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Tipo de participación
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960 |
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Lugar del congreso
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Tunisia |
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Revisores
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Si |
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ISBN o ISSN
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978-1-4244-5091-6 |
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DOI
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Fecha inicio congreso
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13/12/2009 |
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Fecha fin congreso
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16/12/2009 |
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Desde la página
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423 |
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Hasta la página
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426 |
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Título de las actas
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2009 16th IEEE International Conference On Electronics, Circuits and Systems |