Observatorio de I+D+i UPM

Memorias de investigación
Ponencias en congresos:
Architectural Synthesis of DSP Circuits under Simultaneous Error and Time Constraints
Año:2010
Áreas de investigación
  • Microelectrónica
Datos
Descripción
In this paper, the design tasks of wordlength optimization and architectural synthesis are combined. The benefits in comparison to the traditional sequential application of these two tasks are shown. A fine-grain combined wordlength optimization and architectural synthesis based on the use of simulated annealing is presented. As a result, a wider exploration of the design space is possible, thus reducing the implementation costs. The optimizer is tuned for DSP algorithms and is able to simultaneously optimize in terms of implementation area and output noise, thus leading to significant improvements. Moreover, heterogeneous-architecture FPGAs are addressed and the optimization is performed considering both look-up tables (LUTs) and embedded DSP resources. A complete comparison between the traditional sequential approach and the proposed combined approach is provided for FPGAs with and without DSP blocks. Area improvements of up to 21% are reported.
Internacional
Si
Nombre congreso
IEEE/IFIP International Conference on VLSI and System-on-Chip
Tipo de participación
960
Lugar del congreso
Madrid (España)
Revisores
Si
ISBN o ISSN
978-1-4244-6469-2
DOI
10.1109/VLSISOC.2010.5642681
Fecha inicio congreso
27/09/2010
Fecha fin congreso
29/09/2010
Desde la página
322
Hasta la página
327
Título de las actas
Proceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC'10
Esta actividad pertenece a memorias de investigación
Participantes
  • Autor: Gabriel Caffarena Fernandez (UPM)
  • Autor: Carlos Carreras Vaquer (UPM)
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica
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