Observatorio de I+D+i UPM

Descripción
The large size of the attack space that needs to be processed for protection purposes by the participants in a communication over TCP/IP increases the complexity of the processing phase. This processing is even more complicated because of the nature and diversified manifestations of the attacks. Conceptually it is possible to constrict the attack space. The method aimed at such constriction is the motivation behind this work. It is based on hardware processing engines, capable of sustaining high throughput rates of up to 40 Gbps when implemented in an FPGA platform. In its current state, the core presented processes and verifies the TCP/IP reassembly mechanism, eliminating all the potential threats that might arise from the misuse of this TCP/IP specific mechanism.
Internacional	Si
Nombre congreso	International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'07
Tipo de participación	960
Lugar del congreso	Las Vegas (Nevada, USA),
Revisores	Si
ISBN o ISSN	1-60132-026-4
DOI
Fecha inicio congreso	25/06/2007
Fecha fin congreso	28/06/2007
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Título de las actas

Esta actividad pertenece a memorias de investigación

• Autor: Slobodan Bojanic Antonijevic (UPM)
• Autor: Carlos Carreras Vaquer (UPM)
• Autor: Vukasin Pejovic . (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Departamento: Ingeniería Electrónica