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Descripción
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| The large size of the attack space that needs to be processed for protection purposes by the participants in a communication over TCP/IP increases the complexity of the processing phase. This processing is even more complicated because of the nature and diversified manifestations of the attacks. Conceptually it is possible to constrict the attack space. The method aimed at such constriction is the motivation behind this work. It is based on hardware processing engines, capable of sustaining high throughput rates of up to 40 Gbps when implemented in an FPGA platform. In its current state, the core presented processes and verifies the TCP/IP reassembly mechanism, eliminating all the potential threats that might arise from the misuse of this TCP/IP specific mechanism. | |
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Internacional
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Si |
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Nombre congreso
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International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'07 |
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Tipo de participación
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960 |
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Lugar del congreso
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Las Vegas (Nevada, USA), |
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Revisores
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Si |
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ISBN o ISSN
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1-60132-026-4 |
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DOI
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Fecha inicio congreso
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25/06/2007 |
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Fecha fin congreso
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28/06/2007 |
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Título de las actas
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