Observatorio de I+D+i UPM
• ESPAÑOL
• ENGLISH
RESEARCHERS
RDI STRUCTURES
RESEARCH ACTIVITIES
INNOVATION
Investigador
Carlos Carreras Vaquer
Researcher Category
CATEDRATICO UNIVERSIDAD
Role
SUBDIRECTOR DE DEPARTAMENTO.
UPM Centre
E.T.S. DE INGENIEROS DE TELECOMUNICACION
Department:
INGENIERÍA ELECTRÓNICA (N)
Research Centre/Institute
CENTRO I+D+I PROC. INFORMACIÓN Y TELECOM
Knowledge Area
TECNOLOGIA ELECTRONICA
Research Group:
Laboratorio de Sistemas Integrados (LSI)
Email
carlos.carreras
upm.es
Phone
910672204
Research Reports
Proyectos de I+D+i y generación de recursos
32 Proyectos de I+D+i
1: (2007)
AMEBA 3. Transceptores Multielemento y Monocircuito para Radiocomunicación Multimedia de Banda Ancha y Muy Ancha - Diseño Microelectrónico
2: (2007)
FASTMATCH: Framework Architecture to Semantically Integrate Advanced Thread Detection and Security Protection at Ultra-High Speeds
3: (2007)
Segur@
4: (2007)
Sistemas Integrados para Entornos Inteligentes (SINTEI-2)
5: (2007)
Tempus CD-JEP-41107-2006
6: (2008)
AMEBA 3: Transceptores Integrados Multielemento y Monocircuito para Radiocomunicación Digital de Banda Ancha y Muy Ancha. Diseño Electrónico
7: (2008)
Arquitecturas Digitales de Altas Prestaciones
8: (2008)
DOVRES.Design Optimization by Virtual Reality Simulation.
9: (2008)
Proyecto de colaboración TELMAX
10: (2008)
SERVIENDO: Servicios avanzados para personas con problemas de movilidad y comunicación
11: (2009)
ARQUITECTURA DIGITALES DE ALTAS PRESTACIONES
12: (2009)
EC FP6/IST 027095 - FASTMATCH.-
13: (2009)
PEDIDO A8213093 G
14: (2009)
SISTEMAS UWB MULTIELEMENTO Y RECONFIGURABLES PARA APLICACIONES AVANZADAS DE SEÑAL: DISEÑO MICROELECTRONICO
15: (2009)
TELMAX EN EL MARCO DEL PROGRAMA CENIT 2006
16: (2009)
TRANSCEPTORES MULTIELEMENTO Y MONOCIRCUITO PARA RADIOCOMUNICACION MULTIMEDIA DE BANDA ANCHA Y MUY ANCHA - DISEÑO MICROELECTRONICO
17: (2010)
PEDIDO A8213093 G
18: (2010)
SISTEMAS UWB MULTIELEMENTO Y RECONFIGURABLES PARA APLICACIONES AVANZADAS DE SEÑAL: DISEÑO MICROELECTRONICO
19: (2011)
PEDIDO A8213093 G
20: (2011)
PROYECTO CORESIMULAERO
21: (2011)
RAVEN10: Design of Extremely Energy-Efficient Multi-Core Processor in Nanoscale CMOS for Media Processing in Portable Devices
22: (2011)
SISTEMAS UWB MULTIELEMENTO Y RECONFIGURABLES PARA APLICACIONES AVANZADAS DE SEÑAL: DISEÑO MICROELECTRONICO
23: (2012)
DISEÑO DE UN SISTEMA DE PROCESAMIENTO DIGITAL DE SEÑAL PARA LA OPTIMIZACIÓN DE MEDIDAS EN ENTORNOS DE FUSIÓN
24: (2012)
Proyecto AVANZA Competitividad I+D+I CORESIMULAERO
25: (2014)
APPLICATION OF THE MULTISINE SIGNAL TO OBTAIN THE FREQUENCY RESPONSE WITH PSIM
26: (2015)
AMIGA5: El gas en las galaxias y en su entorno. Preparación científica y tecnológica para el SKA Procesado de datos en hardware
27: (2015)
APPLICATION OF THE MULTISINE SIGNAL TO OBTAIN THE FREQUENCY RESPONSE WITH PSIM
28: (2015)
REALIZACIÓN DE UN DISEÑO PARA COMUNICACIÓN SERIE DE MUY ALTA VELOCIDAD UTILIZANDO LOS TRANSCEIVERS DE LAS FPGAS KINTEX-7 DE XILINX
29: (2016)
AMIGA6
30: (2016)
AMIGA6: Gas en el interior y en el entorno de las galaxias, Preparación científica para SKA y contribución al diseño del flujo de datos - Procesado de datos en hardware
31: (2016)
REALIZACIÓN DE UN DISEÑO PARA COMUNICACIÓN SERIE DE MUY ALTA VELOCIDAD UTILIZANDO LOS TRANSCEIVERS DE LAS FPGAS KINTEX-7 DE XILINX
32: (2017)
Red de Excelencia para la participación científica y tecnológica española en el SKA
Formación de Investigadores y Movilidad
5 Tesis Doctorales
1: (2008)
Combined Word-Length Allocation and High-Level Synthesis of Digital Signal Processing Circuits.
2: (2009)
High-Level Power Estimation of DSP Circuits Implemented in FPGAs
3: (2011)
Optimización algorítmica orientada a la implementación en dispositivos reconfigurables de esquemas multiestándar y multiusuario para sincronismo de frecuencia en sistemas de comunicaciones inalámbricas basados en OFDM.
4: (2016)
Automated Word-length Optimization Framework for Multi-source Statistical Interval-based Analysis of Non-linear Systems with Control-flow Structures (Autor: Enrique Sedano Algarabel)
5: (2017)
Compiler and Runtime Support for the Execution of Scientific Codes on Heterogeneous Parallel Architectures
Difusión de Resultados de Investigación
23 Artículos en revistas
1: (2007)
FPGA Acceleration for DNA Sequence Alignment
2: (2007)
Improved Interval-Based Characterization of Fixed-Point LTI Systems with Feedback Loops
3: (2008)
Fast and Accurate Computation of the Round-Off Noise of LTI Systems
4: (2008)
Fast and Accurate Power Estimation of FPGA DSP Components Based on High-level Switching Activity Models
5: (2009)
Architectural Synthesis of Fixed-Point DSP Datapaths
6: (2010)
A Multi-Standard Frequency Offset Synchronization Scheme for 802.11n, 802.16d, LTE and DVB-T/H Systems
7: (2010)
Improved Schemes for Tracking Residual Frequency Offset in DVB-T Systems
8: (2010)
Power Estimation of Embedded Multiplier Blocks in FPGAs
9: (2010)
SQNR Estimation of Fixed-Point DSP Algorithms
10: (2010)
Triple-bit method for power estimation of nonlinear digital circuits in FPGAs
11: (2010)
User Profiling in FPGA for Intrusion Detection Systems
12: (2012)
A complete dynamic power estimation model for data-paths in FPGA DSP designs
13: (2012)
A Reduced Complexity Scheme for Carrier Frequency Synchronization in Uplink 802.16e OFDMA
14: (2012)
A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e OFDMA
15: (2012)
EVALUATION OF RAPID PROTOTYPING SOLUTIONS FOR A 802.16D FREQUENCY OFFSET ESTIMATION SCHEME
16: (2012)
Evaluation of Rapid Prototyping Solutions for a 802.16d Frequency Offset Estimation Scheme
17: (2014)
Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits
18: (2014)
Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes
19: (2015)
A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors
20: (2016)
Acceleration of Simulation-based Techniques for Fixed-point Word-length Selection in DSP Systems
21: (2016)
Dynamic range and round-off noise estimation of fixed-point systems with control-flow structures
22: (2016)
Scalable Modelling of the Fixed-point Round-off Noise through Automatic Clustered Noise Injection
23: (2018)
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs
4 Capítulos de libros
1: (2011)
Applications of Interval-Based Simulations to the Analysis and Design of Digital LTI Systems
2: (2012)
Design and Implementation of Hardware Modules for Baseband Processing in Radio Transceivers: A Case Study
3: (2012)
Fast Fixed-Point Optimization of DSP Algorithms
4: (2012)
Frequency Synchronization for OFDM/OFDMA Systems
1 Conferencias invitadas en congresos
1: (2012)
Turning Control-flow Graphs into Callgraphs - Transformation of Partitioned Codes for Execution in Heterogeneous Architectures
1 Cursos, seminarios y tutoriales
1: (2012)
Turning Control-flow Graphs into Callgraphs - Transformation of Partitioned Codes for Execution in Heterogeneous Architectures
1 Informes para las AAPP o sus organismos dependientes
1: (2013)
Proposal for the Study, Prototyping and Design of the SKA Central Signal Processing Element
2 Libros
1: (2009)
Diseño de Sistemas Digitales con el microcontrolador ColdFire 5272
2: (2017)
Problemas de Sistemas Digitales con el Microcontrolador ColdFire 5272
1 Otras Publicaciones
1: (2014)
Spanish Participation in the CSP Consortium
31 Ponencia en Congresos
1: (2007)
A Comparison of Frequency Offset Synchronization Algorithms for WiMAX OFDM Systems
2: (2007)
A Novel Carrier Frequency Synchronization for WiMAX OFDM Systems
3: (2007)
A TCP/IP Fragmentation Monitoring Core for Intrusion Prevention
4: (2007)
Adding Value to TCP/IP Based Information Exchange Security on Specialised Hardware
5: (2007)
Comparative Evaluation of Carrier Frequency Offset Tracking Schemes for WiMAX OFDM Systems
6: (2007)
High-level Switching Activity Models for Multipliers in FPGAs
7: (2007)
Switching Activity Models for Power Estimation in FPGA Multipliers
8: (2008)
A Comparison of Approaches for High-Level Power Estimation of LUT-based DSP Components
9: (2008)
A Methodology for CFD Acceleration through Reconfigurable Hardware
10: (2008)
Analytical High-level Power model for LUT-based Components
11: (2008)
Optimized Architectural Synthesis of Fixed-Point Datapaths
12: (2009)
A Practical Method for Testing High-speed Networking Hardware Architectures
13: (2009)
Análisis de viabilidad de la implementación de algoritmos CFD en plataformas hardware reconfigurables
14: (2009)
Behavioural Biometrics Hardware Based on Bioinformatics Matching
15: (2009)
Floorplan-based FPGA Interconnect Power Estimation in DSP Circuits
16: (2010)
Adaptive Identification of Nonlinear Multiple-Input Multiple-Output Systems Based on Volterra Models
17: (2010)
Adaptive Identification of Nonlinear Multiple-Input Multiple-Output Systems Based on Volterra Models
18: (2010)
Architectural Synthesis of DSP Circuits under Simultaneous Error and Time Constraints
19: (2010)
Fast and accurate frequency offset tracking scheme for OFDM DVB-T Standard
20: (2010)
Fast Fixed-Point Optimization of DSP Algorithms
21: (2010)
Precision-Wise Architectural Synthesis of DSP Circuits
22: (2010)
SQNR Estimation of Non-Linear Fixed-Point Algorithms
23: (2011)
Interdependency of Fixed-Point Optimization and Architectural Synthesis for Reconfigurable Devices
24: (2011)
Power Estimation of Dividers Implemented in FPGAs
25: (2012)
A Fast Interpolative Wordlength Optimization Method for DSP Systems
26: (2012)
Acceleration of Monte-Carlo Simulation-based Quantization of DSP Systems
27: (2012)
TBT Signal Model for Improved Accuracy of High-level Dynamic Power Estimation Procedure
28: (2012)
Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures
29: (2012)
Use of Multisine Excitations for Frequency-response Measurement of Nonlinear DC-DC Switching Converters
30: (2016)
Interval-based Analysis and Word-length Optimization of Non-linear Systems with Control-flow Structures
31: (2018)
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs
Explotación de Resultados y Transferencia de Tecnología
4 Patentes
1: (2011)
Systems and Methods for Improving the Execution of Computational Algorithms
2: (2011)
Systems and Methods for Improving the Execution of Computational Algorithms
3: (2016)
Systems and Methods for Improving the Execution of Computational Algorithms
4: (2016)
Systems and methods for improving the execution of computational algorithms
• TOMA DE DATOS DE MEMORIAS Y CV
• UPM.ES
S2i 2021 Observatorio de investigación @ UPM con la colaboración del Consejo Social UPM
Cofinanciación del MINECO en el marco del Programa INNPACTO (IPT-020000-2010-22)
